Datasheet

Section 8 DMA Controller (DMAC)
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 281 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
DTC
MAR0A
IOAR0A
ETCR0A
MAR0B
IOAR0B
ETCR0B
MAR1A
IOAR1A
ETCR1A
MAR1B
IOAR1B
ETCR1B
DMATCR
DMACR0B
DMACR1B
DMAWER
DMACR0A
DMACR1A
DMABCR
Second transfer area
using chain transfer
First transfer area
Figure 8.2 Areas for Register Re-Setting by DTC (Example: Channel 0A)
Bit : 7 6 5 4 3 2 1 0
DMAWER : — — — — WE1B WE1A WE0B WE0A
Initial value : 0 0 0 0 0 0 0 0
R/W : — — — — R/W R/W R/W R/W
DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to the
DMACR, DMABCR, and DMATCR by the DTC.
DMAWER is initialized to H'00 by a reset, and in standby mode.
Bits 7 to 4—Reserved: These bits are always read as 0 and cannot be modified.