Datasheet

Section 8 DMA Controller (DMAC)

(This function is not available in the H8S/2695)

Page 282 of 1434 R01UH0166EJ0600 Rev. 6.00

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

Bit 3—Write Enable 1B (WE1B): Enables or disables writes to all bits in DMACR1B, bits 11, 7,

and 3 in DMABCR, and bit 5 in DMATCR by the DTC.

Bit 3

WE1B Description

0 Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR

are disabled (Initial value)

1 Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR

are enabled

Bit 2—Write Enable 1A (WE1A): Enables or disables writes to all bits in DMACR1A, and bits

10, 6, and 2 in DMABCR by the DTC.

Bit 2

WE1A Description

0 Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled

(Initial value)

1 Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled

Bit 1—Write Enable 0B (WE0B): Enables or disables writes to all bits in DMACR0B, bits 9, 5,

and 1 in DMABCR, and bit 4 in DMATCR.

Bit 1

WE0B Description

0 Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR

are disabled (Initial value)

1 Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR

are enabled

Bit 0—Write Enable 0A (WE0A): Enables or disables writes to all bits in DMACR0A, and bits

8, 4, and 0 in DMABCR.

Bit 0

WE0A Description

0 Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled

(Initial value)

1 Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled