Datasheet

Section 8 DMA Controller (DMAC)

(This function is not available in the H8S/2695)

R01UH0166EJ0600 Rev. 6.00 Page 283 of 1434

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the

DMAWER settings. These bits should be changed, if necessary, by CPU processing.

In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0.

To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable

B for the channel to be reactivated.

MAR, IOAR, and ETCR are always write-enabled regardless of the DMAWER settings. When

modifying these registers, the channel for which the modification is to be made should be halted.

8.4.2 DMA Terminal Control Register (DMATCR)

Bit : 7 6 5 4 3 2 1 0

DMATCR : — — TEE1 TEE0 — — — —

Initial value : 0 0 0 0 0 0 0 0

R/W : — — R/W R/W — — — —

DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC

transfer end pin output. A port can be set for output automatically, and a transfer end signal

output, by setting the appropriate bit.

DMATCR is initialized to H'00 by a reset, and in standby mode.

Bits 7 and 6—Reserved: These bits are always read as 0 and cannot be modified.

Bit 5—Transfer End Enable 1 (TEE1): Enables or disables transfer end pin 1 (TEND1) output.

Bit 5

TEE1 Description

0 TEND1 pin output disabled (Initial value)

1 TEND1 pin output enabled

Bit 4—Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 (TEND0) output.

Bit 4

TEE0 Description

0 TEND0 pin output disabled (Initial value)

1 TEND0 pin output enabled