Datasheet

Section 8 DMA Controller (DMAC)

(This function is not available in the H8S/2695)

Page 288 of 1434 R01UH0166EJ0600 Rev. 6.00

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is

incremented or decremented by 1 or 2 each time a byte or word is transferred.

IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of

H'FF.

Figure 8.3 illustrates operation in sequential mode.

Address T

Address B

Transfer

IOAR

1 byte or word transfer performed in

response to 1 transfer request

Legend:

Address T = L

Address B = L + (–1)

DTID

· (2

DTSZ

· (N–1))

Where: L = Value set in MAR

N = Value set in ETCR

Figure 8.3 Operation in Sequential Mode

The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a

transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends.

If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC.

The maximum number of transfers, when H'0000 is set in ETCR, is 65,536.