Datasheet

Section 8 DMA Controller (DMAC)
(This function is not available in the H8S/2695)
Page 298 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Figure 8.9 illustrates operation in single address mode (when sequential mode is specified).
Address T
Address B
Transfer
DAC
K
1 byte or word transfer performed in
response to 1 transfer request
Legend:
Address T = L
Address B = L + (–1)
DTID
· (2
DTSZ
· (N–1))
Where: L = Value set in MAR
N = Value set in ETCR
Figure 8.9 Operation in Single Address Mode (When Sequential Mode is Specified)