Datasheet

Page xxxvi of lvi R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
2.8.5 Bus-Released State ............................................................................................. 91
2.8.6 Power-Down State .............................................................................................. 91
2.9 Basic Timing....................................................................................................................... 92
2.9.1 Overview............................................................................................................. 92
2.9.2 On-Chip Memory (ROM, RAM)........................................................................ 92
2.9.3 On-Chip Supporting Module Access Timing ..................................................... 93
2.9.4 External Address Space Access Timing ............................................................. 95
2.10 Usage Note.......................................................................................................................... 95
2.10.1 TAS Instruction................................................................................................... 95
2.10.2 STM/LDM Instruction........................................................................................ 95
2.10.3 Usage Notes on Bit Manipulation Instructions ................................................... 95
Section 3 MCU Operating Modes
..................................................................................... 97
3.1 Overview ............................................................................................................................ 97
3.1.1 Operating Mode Selection .................................................................................. 97
3.1.2 Register Configuration........................................................................................ 98
3.2 Register Descriptions.......................................................................................................... 98
3.2.1 Mode Control Register (MDCR) ........................................................................ 98
3.2.2 System Control Register (SYSCR)..................................................................... 99
3.2.3 Pin Function Control Register (PFCR) ............................................................. 101
3.3 Operating Mode Descriptions........................................................................................... 104
3.3.1 Mode 4.............................................................................................................. 104
3.3.2 Mode 5.............................................................................................................. 104
3.3.3 Mode 6.............................................................................................................. 104
3.3.4 Mode 7.............................................................................................................. 105
3.4 Pin Functions in Each Operating Mode............................................................................ 105
3.5 Address Map in Each Operating Mode............................................................................. 106
Section 4 Exception Handling .......................................................................................... 111
4.1 Overview .......................................................................................................................... 111
4.1.1 Exception Handling Types and Priority............................................................ 111
4.1.2 Exception Handling Operation ......................................................................... 112
4.1.3 Exception Vector Table .................................................................................... 112
4.2 Reset ................................................................................................................................. 114
4.2.1 Overview........................................................................................................... 114
4.2.2 Types of Reset .................................................................................................. 114
4.2.3 Reset Sequence ................................................................................................. 115
4.2.4 Interrupts after Reset......................................................................................... 117
4.2.5 State of On-Chip Supporting Modules after Reset Release .............................. 118
4.3 Traces................................................................................................................................ 118