Datasheet

Section 8 DMA Controller (DMAC)
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 305 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Figure 8.14 illustrates operation in block transfer mode when MARA is designated as a block area.
Address T
B
Address B
B
Transfer
Address T
A
Address B
A
1st block
2nd block
Nth block
Block area
Consecutive transfer
of M bytes or words
is performed in
response to one
request
Legend:
Address
Address
Address
Address
Where:
= L
A
= L
B
= L
A
+ SAIDE · (–1)
SAID
· (2
DTSZ
· (N–1))
= L
B
+ DAIDE · (–1)
DAID
· (2
DTSZ
· (M·N–1))
= Value set in MARA
= Value set in MARB
= Value set in ETCRB
= Value set in ETCRAH and ETCRAL
T
A
T
B
B
A
B
B
L
A
L
B
N
M
Figure 8.14 Operation in Block Transfer Mode (BLKDIR = 1)