Datasheet

Section 8 DMA Controller (DMAC)
(This function is not available in the H8S/2695)
Page 312 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
8.5.9 Basic DMAC Bus Cycles
An example of the basic DMAC bus cycle timing is shown in figure 8.18. In this example, word-
size transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. When
the bus is transferred from the CPU to the DMAC, a source address read and destination address
write are performed. The bus is not released in response to another bus request, etc., between
these read and write operations. As with CPU cycles, DMA cycles conform to the bus controller
settings.
φ
Address bus
DMAC cycle (1-word transfer)
RD
LWR
HWR
Source
address
Destination address
CPU cycle CPU cycle
T
1
T
2
T
3
T
1
T
2
T
3
T
1
T
2
Figure 8.18 Example of DMA Transfer Bus Timing
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.