Datasheet

R01UH0166EJ0600 Rev. 6.00 Page xxxvii of lvi
Mar 02, 2011
4.4 Interrupts........................................................................................................................... 119
4.5 Trap Instruction................................................................................................................. 120
4.6 Stack Status after Exception Handling.............................................................................. 121
4.7 Notes on Use of the Stack................................................................................................. 122
Section 5 Interrupt Controller ........................................................................................... 123
5.1 Overview........................................................................................................................... 123
5.1.1 Features............................................................................................................. 123
5.1.2 Block Diagram.................................................................................................. 124
5.1.3 Pin Configuration.............................................................................................. 125
5.1.4 Register Configuration...................................................................................... 125
5.2 Register Descriptions........................................................................................................ 126
5.2.1 System Control Register (SYSCR)................................................................... 126
5.2.2 Interrupt Priority Registers A to L, O (IPRA to IPRL, IPRO).......................... 127
5.2.3 IRQ Enable Register (IER) ............................................................................... 128
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL).................................. 129
5.2.5 IRQ Status Register (ISR)................................................................................. 130
5.3 Interrupt Sources............................................................................................................... 131
5.3.1 External Interrupts ............................................................................................ 131
5.3.2 Internal Interrupts.............................................................................................. 132
5.3.3 Interrupt Exception Handling Vector Table...................................................... 132
5.4 Interrupt Operation ........................................................................................................... 142
5.4.1 Interrupt Control Modes and Interrupt Operation............................................. 142
5.4.2 Interrupt Control Mode 0.................................................................................. 146
5.4.3 Interrupt Control Mode 2.................................................................................. 148
5.4.4 Interrupt Exception Handling Sequence ........................................................... 150
5.4.5 Interrupt Response Times ................................................................................. 151
5.5 Usage Notes ...................................................................................................................... 152
5.5.1 Contention between Interrupt Generation and Disabling.................................. 152
5.5.2 Instructions that Disable Interrupts................................................................... 153
5.5.3 Times when Interrupts Are Disabled ................................................................ 153
5.5.4 Interrupts during Execution of EEPMOV Instruction....................................... 154
5.5.5 IRQ Interrupt..................................................................................................... 154
5.5.6 NMI Interrupt Usage Notes............................................................................... 154
5.6 DTC and DMAC Activation by Interrupt
(DMAC and DTC functions are not available in the H8S/2695)...................................... 155
5.6.1 Overview........................................................................................................... 155
5.6.2 Block Diagram.................................................................................................. 156
5.6.3 Operation (DMAC and DTC functions are not available in the H8S/2695) ..... 157