Datasheet

Section 8 DMA Controller (DMAC)
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 321 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
8.5.11 DMAC Bus Cycles (Single Address Mode)
Single Address Mode (Read): Figure 8.27 shows a transfer example in which TEND output is
enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state
access space to an external device.
DMA read
φ
Address bus
DMA
dead
RD
DACK
TEND
Bus
release
DMA read DMA read DMA read
Bus
release
Bus
release
Bus
release
Bus
release
Last transfer
cycle
Figure 8.27 Example of Single Address Mode (Byte Read) Transfer