Datasheet

Page xxxviii of lvi R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
Section 6 PC Break Controller (PBC)
(This function is not available in the H8S/2695) ..................................... 159
6.1 Overview .......................................................................................................................... 159
6.1.1 Features............................................................................................................. 159
6.1.2 Block Diagram.................................................................................................. 160
6.1.3 Register Configuration...................................................................................... 161
6.2 Register Descriptions........................................................................................................ 161
6.2.1 Break Address Register A (BARA).................................................................. 161
6.2.2 Break Address Register B (BARB) .................................................................. 161
6.2.3 Break Control Register A (BCRA) ................................................................... 162
6.2.4 Break Control Register B (BCRB).................................................................... 164
6.2.5 Module Stop Control Register C (MSTPCRC)................................................. 164
6.3 Operation .......................................................................................................................... 165
6.3.1 PC Break Interrupt Due to Instruction Fetch .................................................... 165
6.3.2 PC Break Interrupt Due to Data Access............................................................ 166
6.3.3 Notes on PC Break Interrupt Handling............................................................. 166
6.3.4 Operation in Transitions to Power-Down Modes ............................................. 167
6.3.5 PC Break Operation in Continuous Data Transfer............................................ 168
6.3.6 When Instruction Execution Is Delayed by One State...................................... 169
6.3.7 Additional Notes............................................................................................... 170
Section 7 Bus Controller .................................................................................................... 171
7.1 Overview .......................................................................................................................... 171
7.1.1 Features............................................................................................................. 171
7.1.2 Block Diagram.................................................................................................. 173
7.1.3 Pin Configuration.............................................................................................. 174
7.1.4 Register Configuration...................................................................................... 175
7.2 Register Descriptions........................................................................................................ 176
7.2.1 Bus Width Control Register (ABWCR)............................................................ 176
7.2.2 Access State Control Register (ASTCR) .......................................................... 177
7.2.3 Wait Control Registers H and L (WCRH, WCRL)........................................... 178
7.2.4 Bus Control Register H (BCRH) ...................................................................... 181
7.2.5 Bus Control Register L (BCRL) ....................................................................... 184
7.2.6 Pin Function Control Register (PFCR) ............................................................. 186
7.2.7 Memory Control Register (MCR)
*
................................................................... 189
7.2.8 DRAM Control Register (DRAMCR)
*
............................................................ 191
7.2.9 Refresh Timer Counter (RTCNT)
*
................................................................... 193
7.2.10 Refresh Time Constant Register (RTCOR)
*
.................................................... 193
7.3 Overview of Bus Control.................................................................................................. 194
7.3.1 Area Partitioning............................................................................................... 194