Datasheet

R01UH0166EJ0600 Rev. 6.00 Page xxxix of lvi
Mar 02, 2011
7.3.2 Bus Specifications............................................................................................. 195
7.3.3 Memory Interfaces............................................................................................ 196
7.3.4 Interface Specifications for Each Area ............................................................. 197
7.3.5 Chip Select Signals ........................................................................................... 198
7.4 Basic Bus Interface ........................................................................................................... 199
7.4.1 Overview........................................................................................................... 199
7.4.2 Data Size and Data Alignment.......................................................................... 199
7.4.3 Valid Strobes..................................................................................................... 201
7.4.4 Basic Timing..................................................................................................... 202
7.4.5 Wait Control ..................................................................................................... 210
7.5 DRAM Interface (This function is not available in the H8S/2695) .................................. 212
7.5.1 Overview........................................................................................................... 212
7.5.2 Setting up DRAM Space................................................................................... 212
7.5.3 Address Multiplexing........................................................................................ 213
7.5.4 Data Bus............................................................................................................ 213
7.5.5 DRAM Interface Pins ....................................................................................... 214
7.5.6 Basic Timing..................................................................................................... 214
7.5.7 Precharge State Control .................................................................................... 216
7.5.8 Wait Control ..................................................................................................... 217
7.5.9 Byte Access Control ......................................................................................... 219
7.5.10 Burst Operation................................................................................................. 221
7.5.11 Refresh Control................................................................................................. 225
7.6 DMAC Single Address Mode and DRAM Interface
(This function is not available in the H8S/2695) .............................................................. 229
7.6.1 DDS=1 .............................................................................................................. 229
7.6.2 DDS=0 .............................................................................................................. 230
7.7 Burst ROM Interface......................................................................................................... 231
7.7.1 Overview........................................................................................................... 231
7.7.2 Basic Timing..................................................................................................... 231
7.7.3 Wait Control ..................................................................................................... 233
7.8 Idle Cycle.......................................................................................................................... 234
7.8.1 Operation .......................................................................................................... 234
7.8.2 Pin States in Idle Cycle ..................................................................................... 238
7.9 Write Data Buffer Function .............................................................................................. 239
7.10 Bus Release....................................................................................................................... 240
7.10.1 Overview........................................................................................................... 240
7.10.2 Operation .......................................................................................................... 240
7.10.3 Pin States in External Bus Released State......................................................... 241
7.10.4 Transition Timing ............................................................................................. 242
7.10.5 Notes ................................................................................................................. 243