Datasheet

Section 9 Data Transfer Controller (DTC)
(This function is not available in the H8S/2695)
Page 340 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
9.1.2 Block Diagram
Figure 9.1 shows a block diagram of the DTC.
The DTC’s register information is stored in the on-chip RAM
*
. A 32-bit bus connects the DTC to
the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register
information.
Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
Interrupt
request
Interrupt controller DTC
Internal address bus
DTC service
request
Control logic
Register information
MRA MRB
CRA CRB
DAR SAR
CPU interrupt
request
On-chip
RAM
Internal data bus
Legend:
MRA, MRB:
CRA, CRB:
SAR:
DAR:
DTCERA to DTCERF,
DTCERI:
DTVECR:
DTCERA to
DTCERF,
DTCERI
DTVECR
DTC mode registers A and B
DTC transfer count registers A and B
DTC source address register
DTC destination address register
DTC enable registers A to F and I
DTC vector register
Figure 9.1 Block Diagram of DTC