Datasheet

Section 9 Data Transfer Controller (DTC)
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 341 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
9.1.3 Register Configuration
Table 9.1 summarizes the DTC registers.
Table 9.1 DTC Registers
Name Abbreviation R/W Initial Value Address
*
1
DTC mode register A MRA —
*
2
Undefined —
*
3
DTC mode register B MRB —
*
2
Undefined —
*
3
DTC source address register SAR —
*
2
Undefined —
*
3
DTC destination address register DAR —
*
2
Undefined —
*
3
DTC transfer count register A CRA —
*
2
Undefined —
*
3
DTC transfer count register B CRB —
*
2
Undefined —
*
3
DTC enable registers DTCER R/W H'00 H'FE16 to H'FE1E
DTC vector register DTVECR R/W H'00 H'FE1F
Module stop control register MSTPCRA R/W H'3F H'FDE8
Notes: 1. Lower 16 bits of the address.
2. Registers within the DTC cannot be read or written to directly.
3. Register information is located in on-chip RAM addresses H'EBC0 to H'EFBF. It cannot
be located in external memory space. When the DTC is used, do not clear the RAME
bit in SYSCR to 0.