Datasheet

Page xl of lvi R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
7.11 Bus Arbitration (DMAC and DTC functions are not available in the H8S/2695) ........... 244
7.11.1 Overview........................................................................................................... 244
7.11.2 Operation .......................................................................................................... 244
7.11.3 Bus Transfer Timing......................................................................................... 245
7.12 Resets and the Bus Controller........................................................................................... 245
Section 8 DMA Controller (DMAC)
(This function is not available in the H8S/2695) ..................................... 247
8.1 Overview .......................................................................................................................... 247
8.1.1 Features............................................................................................................. 247
8.1.2 Block Diagram.................................................................................................. 248
8.1.3 Overview of Functions...................................................................................... 249
8.1.4 Pin Configuration.............................................................................................. 251
8.1.5 Register Configuration...................................................................................... 252
8.2 Register Descriptions (1) (Short Address Mode).............................................................. 253
8.2.1 Memory Address Registers (MAR) .................................................................. 254
8.2.2 I/O Address Register (IOAR) ........................................................................... 255
8.2.3 Execute Transfer Count Register (ETCR) ........................................................ 256
8.2.4 DMA Control Register (DMACR) ................................................................... 258
8.2.5 DMA Band Control Register (DMABCR) ....................................................... 262
8.3 Register Descriptions (2) (Full Address Mode)................................................................ 268
8.3.1 Memory Address Register (MAR).................................................................... 268
8.3.2 I/O Address Register (IOAR) ........................................................................... 268
8.3.3 Execute Transfer Count Register (ETCR) ........................................................ 269
8.3.4 DMA Control Register (DMACR) ................................................................... 271
8.3.5 DMA Band Control Register (DMABCR) ....................................................... 275
8.4 Register Descriptions (3) .................................................................................................. 280
8.4.1 DMA Write Enable Register (DMAWER)....................................................... 280
8.4.2 DMA Terminal Control Register (DMATCR) ................................................. 283
8.4.3 Module Stop Control Register (MSTPCR)....................................................... 284
8.5 Operation .......................................................................................................................... 285
8.5.1 Transfer Modes................................................................................................. 285
8.5.2 Sequential Mode ............................................................................................... 287
8.5.3 Idle Mode.......................................................................................................... 290
8.5.4 Repeat Mode..................................................................................................... 293
8.5.5 Single Address Mode........................................................................................ 297
8.5.6 Normal Mode.................................................................................................... 300
8.5.7 Block Transfer Mode........................................................................................ 303
8.5.8 DMAC Activation Sources ............................................................................... 309
8.5.9 Basic DMAC Bus Cycles.................................................................................. 312