Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 120 (14x14) 16-Bit 25 MHz I/O number 73

401

402

403

404

405

406

407

408

409

410

Section 9 Data Transfer Controller (DTC)

(This function is not available in the H8S/2695)

R01UH0166EJ0600 Rev. 6.00 Page 345 of 1434

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

9.2.4 DTC Destination Address Register (DAR)

23 22 21 20 19 43210

Bit

Initial value

—

Unde-

fined

R/W :

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

DAR is a 24-bit register that designates the destination address of data to be transferred by the

DTC. For word-size transfer, specify an even destination address.

9.2.5 DTC Transfer Count Register A (CRA)

15 14 13 12 11109876543210

CRAH CRAL

Bit

Initial value

—

Unde-

fined

R/W :

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.

In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is

decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.

In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits

(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL

functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is

transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is

repeated.