Datasheet

Section 9 Data Transfer Controller (DTC)
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 347 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 9.4, together with the vector number
generated for each interrupt controller.
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and
writing. If all interrupts are masked, multiple activation sources can be set at one time by writing
data after executing a dummy read on the relevant register.
9.2.8 DTC Vector Register (DTVECR)
7
SWDTE
0
R/(W)*
1
6
DTVEC6
0
R/W*
2
5
DTVEC5
0
R/W*
2
4
DTVEC4
0
R/W*
2
3
DTVEC3
0
R/W*
2
0
DTVEC0
0
R/W*
2
2
DTVEC2
0
R/W*
2
1
DTVEC1
0
R/W*
2
Notes: 1. Only 1 can be written to the SWDTE bit.
2. Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.
Bit
Initial value
R/W
:
:
:
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by
software, and sets a vector number for the software activation interrupt.
DTVECR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by
software.
Bit 7
SWDTE Description
0 DTC software activation is disabled (Initial value)
[Clearing conditions]
• When the DISEL bit is 0 and the specified number of transfers have not ended
• When 0 s written to the DISEL bit after a software-activated data transfer end
interrupt (SWDTEND) request has been sent to the CPU
1 DTC software activation is enabled
[Holding conditions]
• When the DISEL bit is 1 and data transfer has ended
• When the specified number of transfers have ended
• During data transfer due to software activation