Datasheet

Section 9 Data Transfer Controller (DTC)
(This function is not available in the H8S/2695)
Page 350 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
The DTC transfer mode can be normal mode, repeat mode, or block transfer mode.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Table 9.2 outlines the functions of the DTC.
Table 9.2 DTC Functions
Address Registers
Transfer Mode Activation Source
Transfer
Source
Transfer
Destination
• Normal mode
⎯ One transfer request transfers one
byte or one word
⎯ Memory addresses are incremented
or decremented by 1 or 2
⎯ Up to 65,536 transfers possible
• Repeat mode
⎯ One transfer request transfers one
byte or one word
⎯ Memory addresses are incremented
or decremented by 1 or 2
⎯ After the specified number of
transfers (1 to 256), the initial state
resumes and operation continues
• Block transfer mode
⎯ One transfer request transfers a bloc
k
of the specified size
⎯ Block size is from 1 to 256 bytes or
words
⎯ Up to 65,536 transfers possible
⎯ A block area can be designated at
either the source or destination
• IRQ
• TPU TGI
• 8-bit timer CMI
• SCI TXI or RXI
• A/D converter ADI
• DMAC DEND
• Software
24 bits 24 bits