Datasheet

Section 9 Data Transfer Controller (DTC)
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 359 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
9.3.6 Repeat Mode
In repeat mode, one operation transfers one byte or one word of data.
From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the
initial state of the transfer counter and the address register specified as the repeat area is restored,
and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and
therefore CPU interrupts cannot be requested when DISEL = 0.
Table 9.6 lists the register information in repeat mode and figure 9.7 shows memory mapping in
repeat mode.
Table 9.6 Register Information in Repeat Mode
Name Abbreviation Function
DTC source address register SAR Designates source address
DTC destination address register DAR Designates destination address
DTC transfer count register AH CRAH Holds number of transfers
DTC transfer count register AL CRAL Designates transfer count
DTC transfer count register B CRB Not used
Transfer
SAR or
DAR
DAR or
SAR
Repeat area
Figure 9.7 Memory Mapping in Repeat Mode