Datasheet

Section 9 Data Transfer Controller (DTC)
(This function is not available in the H8S/2695)
Page 364 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Read Write Read Write
Address
φ
DTC activation
request
DTC
request
Data transfer Data transfer
Transfer
information
write
Transfer
information
write
Transfer
information
read
Transfer
information
read
Vector read
Figure 9.12 DTC Operation Timing (Example of Chain Transfer)
9.3.10 Number of DTC Execution States
Table 9.8 lists execution statuses for a single DTC data transfer, and table 9.9 shows the number
of states required for each execution status.
Table 9.8 DTC Execution Statuses
Mode
Vector Read
(I)
Register Information
Read/Write
(J)
Data Read
(K)
Data Write
(L)
Internal
Operations
(M)
Normal 1 6 1 1 3
Repeat 1 6 1 1 3
Block transfer 1 6 N N 3
N: Block size (initial setting of CRAH and CRAL)