Datasheet

Section 10A I/O Ports
(H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
R01UH0166EJ0600 Rev. 6.00 Page 393 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Port 3 Data Direction Register (P3DDR)
7
P37DDR
0
W
Bit :
Initial value :
R/W :
6
P36DDR
0
W
5
P35DDR
0
W
4
P34DDR
0
W
3
P33DDR
0
W
2
P32DDR
0
W
1
P31DDR
0
W
0
P30DDR
0
W
P3DDR is an 8-bit write-dedicated register, which specifies the I/O for each port 3 pin by bit.
Read is disenabled. If a read is carried out, undefined values are read out.
By setting P3DDR to 1, the corresponding port 3 pins become output, and be clearing to 0 they
become input.
P3DDR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous
state is maintained by a manual reset and in software standby mode. In manual reset SCI and IIC
are initialized, so the pin state is determined by the specification of P3DDR and P3DR.
Port 3 Data Register (P3DR)
7
P37DR
0
R/W
Bit :
Initial value :
R/W :
6
P36DR
0
R/W
5
P35DR
0
R/W
4
P34DR
0
R/W
3
P33DR
0
R/W
2
P32DR
0
R/W
1
P31DR
0
R/W
0
P30DR
0
R/W
P3DR is an 8-bit readable/writable register, which stores the output data of port 3 pins (P35 to
P30).
P3DR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous state
is maintained by a manual reset and in software standby mode.
Port 3 Register (PORT3)
7
P37
—*
R
Bit :
Initial value :
R/W :
6
P36
—*
R
5
P35
—*
R
4
P34
—*
R
3
P33
—*
R
2
P32
—*
R
1
P31
—*
R
0
P30
—*
R
Note: * Determined by the state of pins P37 to P30.