Datasheet

Section 10A I/O Ports
(H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
R01UH0166EJ0600 Rev. 6.00 Page 401 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
10A.5.2 Register Configuration
Table 10A.7 shows the port 7 register configuration.
Table 10A.7 Port 7 Register Configuration
Name Abbreviation R/W Initial Value Address
*
Port 7 data direction register P7DDR W H'00 H'FE36
Port 7 data register P7DR R/W H'00 H'FF06
Port 7 register PORT7 R Undefined H'FFB6
Note: * Lower 16 bits of the address.
Port 7 Data Direction Register (P7DDR)
7
P77DDR
0
W
Bit :
Initial value :
R/W :
6
P76DDR
0
W
5
P75DDR
0
W
4
P74DDR
0
W
3
P73DDR
0
W
2
P72DDR
0
W
1
P71DDR
0
W
0
P70DDR
0
W
P7DDR is an 8-bit write-dedicated register, which specifies the I/O for each port 7 pin by bit.
Read is disenabled. If a read is carried out, undefined values are read out.
By setting P7DDR to 1, the corresponding port 7 pins become output, and by clearing to 0 they
become input.
P7DDR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous
state is maintained by a manual reset and in software standby mode. DMAC, 8-bit timer and SCI
are initialized by a manual reset, so the pin state is determined by the specification of P7DDR and
P7DR.