Datasheet

Section 10A I/O Ports
(H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Page 402 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Port 7 Data Register (P7DR)
7
P77DR
0
R/W
Bit :
Initial value :
R/W :
6
P76DR
0
R/W
5
P75DR
0
R/W
4
P74DR
0
R/W
3
P73DR
0
R/W
2
P72DR
0
R/W
1
P71DR
0
R/W
0
P70DR
0
R/W
P7DR is an 8-bit readable/writable register, which stores the output data of port 7 pins (P77 to
P70).
P7DR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous state
is maintained by a manual reset and in software standby mode.
Port 7 Register (PORT7)
7
P77
—*
R
Bit :
Initial value :
R/W :
6
P76
—*
R
5
P75
—*
R
4
P74
—*
R
3
P73
—*
R
2
P72
—*
R
1
P71
—*
R
0
P70
—*
R
Note: * Determined by the state of pins P77 to P70.
PORT7 is an 8-bit read-dedicated register, which reflects the state of pins. Write is disenabled.
Always carry out writing off output data of port 7 pins (P77 to P70) to P7DR without fail.
When P7DDR is set to 1, if PORT7 is read, the values of P7DR are read. When P7DDR is cleared
to 0, if PORT7 is read, the states of pins are read out.
P7DDR and P7DR are initialized by a power-on reset and in hardware standby mode, so PORT7 is
determined by the state of the pins. The previous state is maintained by a manual reset and in
software standby mode.