Datasheet

Page xlvi of lvi R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
12.1.4 Registers ........................................................................................................... 640
12.2 Register Descriptions........................................................................................................ 641
12.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................ 641
12.2.2 Output Data Registers H and L (PODRH, PODRL)......................................... 642
12.2.3 Next Data Registers H and L (NDRH, NDRL)................................................. 643
12.2.4 Notes on NDR Access ...................................................................................... 643
12.2.5 PPG Output Control Register (PCR) ................................................................ 645
12.2.6 PPG Output Mode Register (PMR) .................................................................. 647
12.2.7 Port 1 Data Direction Register (P1DDR).......................................................... 650
12.2.8 Module Stop Control Register A (MSTPCRA) ................................................ 650
12.3 Operation .......................................................................................................................... 651
12.3.1 Overview........................................................................................................... 651
12.3.2 Output Timing .................................................................................................. 652
12.3.3 Normal Pulse Output ........................................................................................ 653
12.3.4 Non-Overlapping Pulse Output......................................................................... 655
12.3.5 Inverted Pulse Output ....................................................................................... 658
12.3.6 Pulse Output Triggered by Input Capture......................................................... 659
12.4 Usage Notes...................................................................................................................... 659
Section 13 8-Bit Timers (TMR)
(This function is not available in the H8S/2695) ................................... 661
13.1 Overview .......................................................................................................................... 661
13.1.1 Features............................................................................................................. 661
13.1.2 Block Diagram.................................................................................................. 662
13.1.3 Pin Configuration.............................................................................................. 663
13.1.4 Register Configuration...................................................................................... 664
13.2 Register Descriptions........................................................................................................ 665
13.2.1 Timer Counters 0 to 3 (TCNT0 to TCNT3)...................................................... 665
13.2.2 Time Constant Registers A0 to A3 (TCORA0 to TCORA3)............................ 665
13.2.3 Time Constant Registers B0 to B3 (TCORB0 to TCORB3) ............................ 666
13.2.4 Timer Control Registers 0 to 3 (TCR0 to TCR3) ............................................. 666
13.2.5 Timer Control/Status Registers 0 to 3 (TCSR0 to TCSR3) .............................. 669
13.2.6 Module Stop Control Register A (MSTPCRA) ................................................ 672
13.3 Operation .......................................................................................................................... 673
13.3.1 TCNT Incrementation Timing .......................................................................... 673
13.3.2 Compare Match Timing.................................................................................... 674
13.3.3 Timing of External RESET on TCNT .............................................................. 676
13.3.4 Timing of Overflow Flag (OVF) Setting .......................................................... 676
13.3.5 Operation with Cascaded Connection............................................................... 677
13.4 Interrupts........................................................................................................................... 678