Datasheet

Section 10A I/O Ports
(H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
R01UH0166EJ0600 Rev. 6.00 Page 419 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Port B MOS Pull-Up Control Register (PBPCR)
Bit : 7 6 5 4 3 2 1 0
PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port B on an individual bit basis.
In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the TPU’s
TIOR, and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for
that pin.
In mode 7, if a pin is in the input state in accordance with the settings in the TPU’s TIOR and in
DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin.
PBPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.
Port B Open Drain Control Register (PBODR)
Bit : 7 6 5 4 3 2 1 0
PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR
Initial value : 0 0 0 0 0 0 0 0
R/W : R/W R/W R/W R/W R/W R/W R/W R/W
PBODR is an 8-bit readable/writable register that controls the PMOS on/off state for each port B
pin (PB7 to PB0).
When pins are not address outputs in accordance with the setting of bits AE3 to AE0 in PFCR,
setting a PBODR bit makes the corresponding port B pin an NMOS open-drain output, while
clearing the bit to 0 makes the pin a CMOS output.
PBODR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.