Datasheet

Section 10A I/O Ports
(H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
R01UH0166EJ0600 Rev. 6.00 Page 423 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Pin Selection Method and Pin Functions
PB5/A13/TIOCB4 The function of this pin changes according to the operating mode and the
setting of bits AE3 to AE0 in PFCR; the TPU4 settings of bits MD3 to MD0 in
TMDR4, bits IOB3 to IOB0 in TIOR4, and the CCLR1 and CCLR0 bits in
TCR4; and the setting of the PB5DDR bit.
Operating
Mode
Modes 4 to 6
AE3 to AE0 B'0000 to B'0101
B'0110 to
B'1111
TPU Channel
4 Setting
Table Below (1) Table Below (2) —
PB5DDR — 0 1 —
PB5 input PB5 output Pin function TIOCB4 output
TIOCB4 input
*
A13 output
Operating
Mode
Mode 7
TPU Channel
4 Setting
Table Below (1) Table Below (2)
PB5DDR — 0 1
PB5 input PB5 output Pin function TIOCB4 output
TIOCB4 input
*
TPU Channel
4 Setting
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB3 to IOB0 B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
— B'xx00 Other than B'xx00
CCLR1,
CCLR0
— — — —
Other
than
B'10
B'10
Output
function
—
Output
compare
output
— —
PWM
mode 2
output
—
x: Don't care
Note: TIOCB4 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0
= B'10xx.