Datasheet

Section 10A I/O Ports
(H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Page 438 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
10A.10.2 Register Configuration
Table 10A.18 shows the port D register configuration.
Table 10A.18 Port D Registers
Name Abbreviation R/W Initial Value Address
*
Port D data direction register PDDDR W H'00 H'FE3C
Port D data register PDDR R/W H'00 H'FF0C
Port D register PORTD R Undefined H'FFBC
Port D MOS pull-up control register PDPCR R/W H'00 H'FE43
Note: * Lower 16 bits of the address.
Port D Data Direction Register (PDDDR)
Bit : 7 6 5 4 3 2 1 0
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
Initial value : 0 0 0 0 0 0 0 0
R/W : W W W W W W W W
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.
PDDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state by a manual reset or in software standby mode.
• Modes 4 to 6
The input/output direction specification by PDDDR is ignored, and port D is automatically
designated for data I/O.
• Mode 7
Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing
the bit to 0 makes the pin an input port.