Datasheet

Page l of lvi R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
18.3.1 I
2
C Bus Data Format ......................................................................................... 866
18.3.2 Initial Setting .................................................................................................... 868
18.3.3 Master Transmit Operation............................................................................... 868
18.3.4 Master Receive Operation................................................................................. 872
18.3.5 Slave Receive Operation................................................................................... 878
18.3.6 Slave Transmit Operation ................................................................................. 883
18.3.7 IRIC Setting Timing and SCL Control ............................................................. 886
18.3.8 Operation Using the DTC
*
............................................................................... 887
18.3.9 Noise Canceler.................................................................................................. 888
18.3.10 Initialization of Internal State ........................................................................... 889
18.4 Usage Notes...................................................................................................................... 890
Section 19 A/D Converter
.................................................................................................. 903
19.1 Overview .......................................................................................................................... 903
19.1.1 Features............................................................................................................. 903
19.1.2 Block Diagram.................................................................................................. 904
19.1.3 Pin Configuration.............................................................................................. 905
19.1.4 Register Configuration...................................................................................... 906
19.2 Register Descriptions........................................................................................................ 907
19.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .......................................... 907
19.2.2 A/D Control/Status Register (ADCSR) ............................................................ 908
19.2.3 A/D Control Register (ADCR) ......................................................................... 911
19.2.4 Module Stop Control Register A (MSTPCRA) ................................................ 912
19.3 Interface to Bus Master..................................................................................................... 913
19.4 Operation .......................................................................................................................... 914
19.4.1 Single Mode (SCAN = 0) ................................................................................. 914
19.4.2 Scan Mode (SCAN = 1).................................................................................... 916
19.4.3 Input Sampling and A/D Conversion Time ...................................................... 918
19.4.4 External Trigger Input Timing.......................................................................... 919
19.5 Interrupts........................................................................................................................... 920
19.6 Usage Notes...................................................................................................................... 921
Section 20 D/A Converter
(This function is not available in the H8S/2695) ................................... 927
20.1 Overview .......................................................................................................................... 927
20.1.1 Features............................................................................................................. 927
20.1.2 Block Diagram.................................................................................................. 928
20.1.3 Input and Output Pins ....................................................................................... 929
20.1.4 Register Configuration...................................................................................... 929
20.2 Register Descriptions........................................................................................................ 930