Datasheet

Section 10A I/O Ports
(H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
R01UH0166EJ0600 Rev. 6.00 Page 455 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
When the DRAM interface is set, pin PG0 functions as the CAS output pin. When PGDDR is
set to 1, the pin functions as an output port. When PGDDR is cleared to 0, the pin functions as
an input port.
See section 7, Bus Controller, for the DRAM interface.
• Mode 7
PGDDR to 1 it becomes an output port, and by clearing it to 0 it becomes an input port.
Port G Data Register (PGDR)
7
—
Undefined
—
Bit :
Initial value :
R/W :
6
—
Undefined
—
5
—
Undefined
—
4
PG4DR
0
R/W
3
PG3DR
0
R/W
2
PG2DR
0
R/W
1
PG1DR
0
R/W
0
PG0DR
0
R/W
PGDR is an 8-bit read/write register and stores output data of port G output pins (PG4 to PG0).
Bits 7 to 5 are reserved bits. When the contents are read, undefined values are read. Write
processing is invalid.
In power-on reset or hardware standby mode, PGDR is initialized to H'00 (bits 4 to 0). In manual
reset or software standby mode, PGDR retains the last state.
(3) Port G Register (PORTG)
7
—
Undefined
—
Bit :
Initial value :
R/W :
6
—
Undefined
—
5
—
Undefined
—
4
PG4
—*
R
3
PG3
—*
R
2
PG2
—*
R
1
PG1
—*
R
0
PG0
—*
R
Note: * Determined by the state of PG4 to PG0
PORTG is an 8-bit read only register and reflects the pin state. Write processing is invalid. Write
processing of output data of port G pins (PG4 to PG0) must be performed for PGDR.
Bits 7 to 5 are reserved bits. When the contents are read, undefined values are read. Write
processing is invalid.
If PORTG is read when PGDDR is set to 1, the value in PGDR is read. If PORTG is read when
PGDDR is cleared to 0, the pin state is read.