Datasheet

Section 10A I/O Ports
(H8S/2633, H8S/2632, H8S/2631, H8S/2633R)
Page 456 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
In power-on reset or hardware standby mode, port G is determined by the pin state because
PGDDR and PGDR are initialized. In manual reset or software standby mode, the last state is
retained.
10A.13.3 Pin Functions
Port G is used also as external interrupt input pins (IRQ6 and IRQ7) and bus control signal output
pins (CS0 to CS3, CAS, and OE). The pin functions are different between modes 4 and 6, and
mode 7. Table 10A.25 shows the port G pin functions.
Table 10A.25 Port G Pin Functions
Pin Selection Method and Pin Functions
PG4/CS0 The pin function is switched as shown below according to the operating mode and
bit PG4DDR.
Operating
Mode
Modes 4 to 6 Mode 7
PG4DDR 0 1 0 1
Pin function PG4 input pin CS0 output pin PG4 input pin PG4 output pin
PG3/CS1 The pin function is switched as shown below according to the operating mode and
bit PG3DDR.
Operating
Mode
Modes 4 to 6 Mode 7
PG3DDR 0 1 0 1
Pin function PG3 input pin CS1 output pin PG3 input pin PG3 output pin
PG2/CS2 The pin function is switched as shown below according to the operating mode and
bit PG2DDR.
Operating
Mode
Modes 4 to 6 Mode 7
PG2DDR 0 1 0 1
Pin function PG2 input pin CS2 output pin PG2 input pin PG2 output pin