Datasheet

Section 10B I/O Ports
(H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 481 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Port 3 Register (PORT3)
7
P37
—*
R
Bit :
Initial value :
R/W :
6
P36
—*
R
5
P35
—*
R
4
P34
—*
R
3
P33
—*
R
2
P32
—*
R
1
P31
—*
R
0
P30
—*
R
Note: * Determined by the state of pins P37 to P30.
PORT3 is an 8-bit read-dedicated register, which reflects the state of pins. Write is disenabled.
Always carry out writing off output data of port 3 pins (P37 to P30) to P3DR without fail.
When P3DDR is set to 1, if PORT3 is read, the values of P3DR are read. When P3DDR is cleared
to 0, if PORT3 is read, the states of pins are read out.
P3DDR and P3DR are initialized by a power-on reset and in hardware standby mode, so PORT3 is
determined by the state of the pins. The previous state is maintained by a manual reset and in
software standby mode.
Port 3 Open Drain Control Register (P3ODR)
7
P37ODR
0
R/W
Bit
Initial value
R/W
:
:
:
6
P36ODR
0
R/W
5
P35ODR
0
R/W
4
P34ODR
0
R/W
3
P33ODR
0
R/W
2
P32ODR
0
R/W
1
P31ODR
0
R/W
0
P30ODR
0
R/W
P3ODR is an 8-bit readable/writable register, which controls the on/off of port 3 pins (P37 to
P30).
By setting P3ODR to 1, the port 3 pins become an open drain out, and when cleared to 0 they
become CMOS output.
P3ODR is initialized to H'00 by a power-on reset and in hardware standby mode. The previous
state is maintained by a manual reset and in software standby mode.