Datasheet

Section 10B I/O Ports
(H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 495 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
10B.7.2 Register Configuration
Table 10B.10 shows the port A register configuration.
Table 10B.10 Port A Registers
Name Abbreviation R/W Initial Value
*
2
Address
*
1
Port A data direction register PADDR W H'0 H'FE39
Port A data register PADR R/W H'0 H'FF09
Port A register PORTA R Undefined H'FFB9
Port A MOS pull-up control register PAPCR R/W H'0 H'FE40
Port A open-drain control register PAODR R/W H'0 H'FE47
Notes: 1. Lower 16 bits of the address.
2. Value of bits 3 to 0.
Port A Data Direction Register (PADDR)
Bit : 7 6 5 4 3 2 1 0
— — — — PA3DDR PA2DDR PA1DDR PA0DDR
Initial value : Undefined Undefined Undefined Undefined 0 0 0 0
R/W : — — — — W W W W
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read.
Bits 7 and 6 are reserved; they return an undetermined value if read.
PADDR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state by a manual reset or in software standby mode. The OPE bit in SBYCR is
used to select whether the address output pins retain their output state or become high-impedance
when a transition is made to software standby mode. See section 24.2.1, Standby Control Register
(SBYCR), for details.
• Modes 4 to 6
The corresponding port A pins become address outputs in accordance with the setting of bits
AE3 to AE0 in PFCR, irrespective of the value of bits PA4DDR to PA0DDR. When pins are
not used as address outputs, setting a PADDR bit to 1 makes the corresponding port A pin an
output port, while clearing the bit to 0 makes the pin an input port.