Datasheet

Section 10B I/O Ports
(H8S/2695)
Page 496 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
• Mode 7
Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing
the bit to 0 makes the pin an input port.
Port A Data Register (PADR)
Bit : 7 6 5 4 3 2 1 0
— — — — PA3DR PA2DR PA1DR PA0DR
Initial value : Undefined Undefined Undefined Undefined 0 0 0 0
R/W : — — — — R/W R/W R/W R/W
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA3 to
PA0).
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
PADR is initialized to H'0 (bits 3 to 0) by a powr-on reset, and in hardware standby mode. It
retains its prior state by a manual reset or in software standby mode.
Port A Register (PORTA)
Bit : 7 6 5 4 3 2 1 0
— — — — PA3 PA2 PA1 PA0
Initial value : Undefined Undefined Undefined Undefined —
*
—
*
—
*
—
*
R/W : — — — — R R R R
Note: * Determined by state of pins PA3 to PA0.
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port A pins (PA3 to PA0) must always be performed on PADR.
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
If a PORTA read is performed while PADDR bits are set to 1, the PADR values are read. If a
PORTA read is performed while PADDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTA contents are determined by the pin
states, as PADDR and PADR are initialized. PORTA retains its prior state by a manual reset or in
software standby mode.