Datasheet

Section 1 Overview
Page 2 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Table 1.1 Overview
Item Specification
CPU
• General-register machine
⎯ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers
or eight 32-bit registers)
• High-speed operation suitable for realtime control
⎯ Maximum clock rate: 25 MHz (H8S/2633 Group, H8S/2633F),
28 MHz (H8S/2633R, H8S/2695)
⎯ High-speed arithmetic operations
8/16/32-bit register-register add/subtract : 40 ns, 35 ns
16 × 16-bit register-register multiply : 160 ns, 140 ns
16 × 16 + 42-bit multiply and accumulate : 160 ns, 140 ns
32 ÷ 16-bit register-register divide : 800 ns, 700 ns
• Instruction set suitable for high-speed operation
⎯ Sixty-nine basic instructions
⎯ 8/16/32-bit move/arithmetic and logic instructions
⎯ Unsigned/signed multiply and divide instructions
⎯ Multiply-and accumulate instruction
⎯ Powerful bit-manipulation instructions
• Two CPU operating modes
⎯ Normal mode: 64-kbyte address space
(cannot be used in the H8S/2633 Group)
⎯ Advanced mode: 16-Mbyte address space
Bus controller
• Address space divided into 8 areas, with bus specifications settable
independently for each area
• Choice of 8-bit or 16-bit access space for each area
• 2-state or 3-state access space can be designated for each area
• Number of program wait states can be set for each area
• Burst ROM directly connectable
• Possible to connect a maximum of 8 MB of DRAM (alternatively, it is also
possible to use an interval timer)
• External bus release function
PC break
controller
*
1
• Supports debugging functions by means of PC break interrupts
• Two break channels