Datasheet

Section 1 Overview
R01UH0166EJ0600 Rev. 6.00 Page 3 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Item Specification
DMA controller
(DMAC)
*
1
• Short address mode and full address mode selectable
• Short address mode: 4 channels
Full address mode: 2 channels
• Transfer possible in repeat mode/block transfer mode
Transfer possible in single address mode
• Activation by internal interrupt possible
Data transfer
controller (DTC)
*
1
• Can be activated by internal interrupt or software
• Multiple transfers or multiple types of transfer possible for one activation
source
• Transfer possible in repeat mode, block transfer mode, etc.
• Request can be sent to CPU for interrupt that activated DTC
16-bit timer-pulse
unit (TPU)
• 6-channel 16-bit timer on-chip
• Pulse I/O processing capability for up to 16 pins'
• Automatic 2-phase encoder count capability
Programmable
pulse generator
(PPG)
*
1
• Maximum 16-bit pulse output possible with TPU as time base
• Output trigger selectable in 4-bit groups
• Non-overlap margin can be set
• Direct output or inverse output setting possible
8-bit timer
*
1
4 channels
• 8-bit up counter (external event count possible)
• Time constant register × 2
• 2 channel connection possible
Watchdog timer
2 channels
*
2
• Watchdog timer or interval timer selectable
• Operation using sub-clock supported (WDT1 only)
14-bit PWM timer
(PWM)
*
1
• Maximum of 4 outputs
• Resolution: 1/16384
• Maximum carrier frequency: 390.6 kHz (operating at 25 MHz),
437.6 kHz (operating at 28 MHz)
Serial
communication
interface (SCI)
5 channels
(SCI0 to SCI4)
• Asynchronous mode or synchronous mode selectable
• Multiprocessor communication function
• Smart card interface function