Datasheet

Section 10B I/O Ports
(H8S/2695)
Page 534 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
10B.12.2 Register Configuration
Table 10B.22 shows the port F register configuration.
Table 10B.22 Port F Registers
Name Abbreviation R/W Initial Value Address
*
1
Port F data direction register PFDDR W H'80/H'00
*
2
H'FE3E
Port F data register PFDR R/W H'00 H'FF0E
Port F register PORTF R Undefined H'FFBE
Notes: 1. Lower 16 bits of the address.
2. Initial value depends on the mode.
Port F Data Direction Register (PFDDR)
Bit : 7 6 5 4 3 2 1 0
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
Modes 4 to 6
Initial value : 1 0 0 0 0 0 0 0
R/W : W W W W W W W W
Mode 7
Initial value : 0 0 0 0 0 0 0 0
R/W : W W W W W W W W
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a power-on reset, and in hardware standby mode, to H'80 in modes 4 to
6, and to H'00 in mode 7. It retains its prior state by a manual reset or in software standby mode.
The OPE bit in SBYCR is used to select whether the bus control output pins retain their output
state or become high-impedance when a transition is made to software standby mode.
• Modes 4 to 6
Pin PF7 functions as the φ output pin when the corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
The input/output direction specified by PFDDR is ignored for pins PF6 to PF3, which are
automatically designated as bus control outputs (AS, RD, HWR, and LWR).