Datasheet

Section 10B I/O Ports
(H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 539 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
10B.13.2 Register Configuration
Table 10B.24 shows the port G register configuration.
Table 10B.24 Port G Registers
Name Abbreviation R/W Initial Value
*
2
Address
*
1
Port G data direction register PGDDR W H'10/H'00
*
3
H'FE3F
Port G data register PGDR R/W H'00 H'FF0F
Port G register PORTG R Undefined H'FFBF
Notes: 1. Lower 16 bits of the address.
2. Value of bits 4 to 0.
3. The initial value varies according to the mode.
Port G Data Direction Register (PGDDR)
7
—
Undefined
—
Bit :
Modes 4 and 5
Initial value :
R/W :
6
—
Undefined
—
5
—
Undefined
—
4
PG4DDR
1
W
3
PG3DDR
0
W
2
PG2DDR
0
W
1
PG1DDR
0
W
0
PG0DDR
0
W
Undefined
—
Modes 6 and 7
Initial value :
R/W :
Undefined
—
Undefined
—
0
W
0
W
0
W
0
W
0
W
PGDDR is an 8-bit write only register and specifies I/O of each pin of port G in bit units. Read
processing is invalid. Bits 7 to 5 are reserved bits. When the contents are read, undefined values
are read.
In modes 4 and 5, the PGDDR bits are initialized to H'10 (bits 4 to 0) in power-on reset or
hardware standby mode, in modes 6 and 7, the bits are initialized to H'00 (bits 4 to 0). In manual
reset or software standby mode, PGDDR retains the last status. Use the OPE bit of SBYCR to
select whether the bus control output pin retains the output state or becomes the high-impedance
when the mode is changed to a software standby mode.
• Modes 4 to 6
When PGDDR is set to 1, pins PG4 to PG1 function as bus control signal output pins (CS0 to
CS3). When PGDDR is cleared to 0, the pins function as input ports.