Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
R01UH0166EJ0600 Rev. 6.00 Page 553 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bits 7, 6, and 5—Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the
TCNT counter clearing source.
Bit 7 Bit 6 Bit 5
Channel CCLR2 CCLR1 CCLR0 Description
0, 3 0 0 0 TCNT clearing disabled (Initial value)
1 TCNT cleared by TGRA compare match/input
capture
1 0 TCNT cleared by TGRB compare match/input
capture
1 TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation
*
1
1 0 0 TCNT clearing disabled
1 TCNT cleared by TGRC compare match/input
capture
*
2
1 0 TCNT cleared by TGRD compare match/input
capture
*
2
1 TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation
*
1
Bit 7 Bit 6 Bit 5
Channel Reserved
*
3
CCLR1 CCLR0 Description
1, 2, 4, 5 0 0 0 TCNT clearing disabled (Initial value)
1 TCNT cleared by TGRA compare match/input
capture
1 0 TCNT cleared by TGRB compare match/input
capture
1 TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation
*
1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
3. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
modified.