Datasheet

Section 1 Overview
R01UH0166EJ0600 Rev. 6.00 Page 5 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Item Specification
Power-down state
• Medium-speed mode
• Sleep mode
• Module stop mode
• Software standby mode
• Hardware standby mode
• Subclock operation
*
1
(subactive mode, subsleep mode, watch mode)
Operating modes Four MCU operating modes
External Data Bus
Mode
CPU
Operating
Mode
Description
On-Chip
ROM
Initial
Value
Maximu
m Value
4 Advanced On-chip ROM disabled
expansion mode
Disabled 16 bits 16 bits
5 On-chip ROM disabled
expansion mode
Disabled 8 bits 16 bits
6 On-chip ROM enabled
expansion mode
Enabled 8 bits 16 bits
7 Single-chip mode Enabled — —
Clock pulse
generator
H8S/2633, H8S/2632, H8S/2631
• On-chip PLL circuit (×1, ×2, ×4)
• Input clock frequency: 2 to 25 MHz
H8S/2633R, H8S/2695
• On-chip PLL circuit (×1, ×2, ×4): 2 to 25 MHz
(×2, ×4): 25 to 28 MHz
• Input clock frequency: 2 to 25 MHz
Packages
• 120-pin plastic TQFP (TFP-120)
• 128-pin plastic QFP (FP-128B)
I
2
C bus interface
(IIC)
*
1
2 channels
(optional)
• Conforms to I
2
C bus interface type advocated by Philips
• Single master mode/slave mode
• Possible to determine arbitration lost conditions
• Supports two slave addresses