Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)

R01UH0166EJ0600 Rev. 6.00 Page 557 of 1434

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

11.2.2 Timer Mode Register (TMDR)

Channel 0: TMDR0

Channel 3: TMDR3

Bit : 7 6 5 4 3 2 1 0

— — BFB BFA MD3 MD2 MD1 MD0

Initial value : 1 1 0 0 0 0 0 0

R/W : — — R/W R/W R/W R/W R/W R/W

Channel 1: TMDR1

Channel 2: TMDR2

Channel 4: TMDR4

Channel 5: TMDR5

Bit : 7 6 5 4 3 2 1 0

— — — — MD3 MD2 MD1 MD0

Initial value : 1 1 0 0 0 0 0 0

R/W : — — — — R/W R/W R/W R/W

The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode

for each channel. The TPU has six TMDR registers, one for each channel. The TMDR registers

are initialized to H'C0 by a reset, and in hardware standby mode.

TMDR register settings should be made only when TCNT operation is stopped.

Bits 7 and 6—Reserved: These bits are always read as 1 and cannot be modified.

Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or

TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer

In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and

cannot be modified.