Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Page 564 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bit 7 Bit 6 Bit 5 Bit 4
Channel IOD3 IOD2 IOD1 IOD0 Description
3 0 0 0 0 Output disabled (Initial value)
1 0 output at compare match
1 0 1 output at compare match
1
TGR3D
is output
compare
register*
2
Initial output is 0
output
Toggle output at compare
match
1 0 0 Output disabled
1 0 output at compare match
1 0 1 output at compare match
1
Initial output is 1
output
Toggle output at compare
match
1 0 0 0 Input capture at rising edge
1 Input capture at falling edge
1 *
Capture input
source is
TIOCD3 pin
Input capture at both edges
1 * *
TGR3D
is input
capture
register
*
2
Capture input
source is channel
4/count clock
Input capture at TCNT4
count-up/count-down
*
1
*: Don't care
Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and φ/1 is used as the TCNT4
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.