Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)

R01UH0166EJ0600 Rev. 6.00 Page 573 of 1434

Mar 02, 2011

H8S/2633 Group, H8S/2633 F-ZTAT

H8S/2633R F-ZTAT

, H8S/2695

Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D

conversion start requests by TGRA input capture/compare match.

Bit 7

TTGE Description

0 A/D conversion start request generation disabled (Initial value)

1 A/D conversion start request generation enabled

Bit 6—Reserved: This bit is always read as 1 and cannot be modified.

Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by

the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5.

In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified.

Bit 5

TCIEU Description

0 Interrupt requests (TCIU) by TCFU disabled (Initial value)

1 Interrupt requests (TCIU) by TCFU enabled

Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by

the TCFV flag when the TCFV flag in TSR is set to 1.

Bit 4

TCIEV Description

0 Interrupt requests (TCIV) by TCFV disabled (Initial value)

1 Interrupt requests (TCIV) by TCFV enabled

Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the

TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3.

In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.

Bit 3

TGIED Description

0 Interrupt requests (TGID) by TGFD bit disabled (Initial value)

1 Interrupt requests (TGID) by TGFD bit enabled