Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
R01UH0166EJ0600 Rev. 6.00 Page 585 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Examples of 8-bit register access operation are shown in figures 11.3, 11.4, and 11.5.
Bus interface
H
Internal data bus
L
Module
data bus
TCR
Bus
master
Figure 11.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)]
Bus interface
H
Internal data bus
L
Module
data bus
TMDR
Bus
master
Figure 11.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)]
Bus interface
H
Internal data bus
L
Module
data bus
TCR TMDR
Bus
master
Figure 11.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)]