Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
R01UH0166EJ0600 Rev. 6.00 Page 625 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC
*
or DMAC
*
is activated, the flag is cleared automatically. Figure 11.46
shows the timing for status flag clearing by the CPU, and figure 11.47 shows the timing for status
flag clearing by the DTC
*
or DMAC
*
.
Note: * DMAC and DTC functions are not available in the H8S/2695.
Status flag
Write signal
Address
φ
TSR address
Interrupt
request
signal
TSR write cycle
T1 T2
Figure 11.46 Timing for Status Flag Clearing by CPU
Interrupt
request
signal
Status flag
Note: * DMAC and DTC functions are not available in the H8S/2695.
Address
φ
Source address
DTC
*
/DMAC
*
read cycle
T1 T2
Destination
address
T1 T2
DTC
*
/DMAC
*
write cycle
Figure 11.47 Timing for Status Flag Clearing by DTC
*
or DMAC
*
Activation