Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
R01UH0166EJ0600 Rev. 6.00 Page 627 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Contention between TCNT Write and Clear Operations: If the counter clear signal is
generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT
write is not performed.
Figure 11.49 shows the timing in this case.
Counter clear
signal
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T1 T2
N H'0000
Figure 11.49 Contention between TCNT Write and Clear Operations