Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
R01UH0166EJ0600 Rev. 6.00 Page 629 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Contention between TGR Write and Compare Match: If a compare match occurs in the T2
state of a TGR write cycle, the TGR write takes precedence and the compare match signal is
inhibited. A compare match does not occur even if the same value as before is written.
Figure 11.51 shows the timing in this case.
Compare
match signal
Write signal
Address
φ
TGR address
TCNT
TGR write cycle
T1 T2
N M
TGR write data
TGR
N N+1
Inhibited
Figure 11.51 Contention between TGR Write and Compare Match