Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Page 630 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the
data prior to the write.
Figure 11.52 shows the timing in this case.
Compare
match signal
Write signal
Address
φ
Buffer register
address
Buffer
register
TGR write cycle
T1 T2
N
TGR
N M
Buffer register write data
Figure 11.52 Contention between Buffer Register Write and Compare Match