Datasheet

Section 12 Programmable Pulse Generator (PPG)
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 651 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
12.3 Operation
12.3.1 Overview
PPG pulse output is enabled when the corresponding bits in P1DDR and NDER are set to 1. In
this state the corresponding PODR contents are output.
When the compare match event specified by PCR occurs, the corresponding NDR bit contents are
transferred to PODR to update the output values.
Figure 12.2 illustrates the PPG output operation and table 12.3 summarizes the PPG operating
conditions.
Output trigger signal
Pulse output pin
Internal data bus
Normal output/inverted output
C
PODRQD
NDER
Q
NDRQD
DDR
Q
Figure 12.2 PPG Output Operation
Table 12.3 PPG Operating Conditions
NDER DDR Pin Function
0 0 Generic input port
1 Generic output port
1 0 Generic input port (but the PODR bit is a read-only bit, and when
compare match occurs, the NDR bit value is transferred to the PODR bit)
1 PPG pulse output
Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the
next compare match. For details of non-overlapping operation, see section 12.3.4, Non-
Overlapping Pulse Output.