Datasheet

Section 13 8-Bit Timers (TMR)
(This function is not available in the H8S/2695)
Page 668 of 1434 R01UH0166EJ0600 Rev. 6.00
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to
TCNT is an internal or external clock.
Three internal clocks can be selected, all divided from the system clock (φ): φ/8, φ/64, and φ/8192.
The falling edge of the selected internal clock triggers the count.
When use of an external clock is selected, three types of count can be selected: at the rising edge,
the falling edge, and both rising and falling edges.
Some functions differ between channel 0 and channel 1.
Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0 Description
0 0 0 Clock input disabled (Initial value)
1 Internal clock, counted at falling edge of φ/8
1 0 Internal clock, counted at falling edge of φ/64
1 Internal clock, counted at falling edge of φ/8192
1 0 0 For channel 0: count at TCNT1 overflow signal
*
For channel 1: count at TCNT0 compare match A
*
For channel 2: count at TCNT3 overflow signal
*
For channel 3: count at TCNT2 compare match A
*
1 External clock, counted at rising edge
1 0 External clock, counted at falling edge
1 External clock, counted at both rising and falling edges
Note: * If the count input of channel 0 (channel 2) is the TCNT1 (TCNT3) overflow signal and that of
channel 1 (channel 3) is the TCNT0 (TCNT2) compare match signal, no incrementing clock
is generated. Do not use this setting.