Datasheet

Section 13 8-Bit Timers (TMR)
(This function is not available in the H8S/2695)
R01UH0166EJ0600 Rev. 6.00 Page 669 of 1434
Mar 02, 2011
H8S/2633 Group, H8S/2633 F-ZTAT
TM
,
H8S/2633R F-ZTAT
TM
, H8S/2695
13.2.5 Timer Control/Status Registers 0 to 3 (TCSR0 to TCSR3)
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
ADTE
0
R/W
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Only 0 can be written to bits 7 to 5, to clear these flags.
Bit
Initial value
R/W
:
:
:
Note: *
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
—
1
—
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Bit
Initial value
R/W
:
:
:
TCSR0
TCSR1, TCSR3
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
—
0
R/W
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Bit
Initial value
R/W
:
:
:
TCSR2
TCSR0 to TCSR3 are 8-bit registers that display compare match and timer overflow statuses, and
control compare match output.
TCSR0 and TCSR2 are initialized to H'00, and TCSR1 and TCSR3 to H'10, by a reset and in
hardware standby mode.